Elimination of Non-Simultaneous Triggering E ects in Finger-type ESD Protection Transistors Using Heterojunction Buried Layer
نویسندگان
چکیده
This paper presents a novel technique to eliminate non-simultaneous triggering e ects in nger-type ESD protection transistor using SiGe heterojunction buried layer structures. It is con rmed that lower snapback voltage and maximum lattice temperature are obtainable in the new structure based on device simulation. As a result, current localization and lattice overheating of a nger-type protection transistor caused by process variations can be avoided in this structure.
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